One example of a prior art full-rail differential logic circuit is presented and discussed at page 112, and shown in FIG. 3(c), in “HIGH SPEED CMOS DESIGN STYLES” by Bernstein et al. of IBM Microelectronics; Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Mass., 02061; ISBN 0-7923-8220-X, hereinafter referred to as the Bernstein et al. reference, which is incorporated herein by reference, in its entirety, for all purposes.
FIG. 1A shows a prior art full-rail differential logic circuit 100 similar to that discussed in the Bernstein et al. reference. As seen in FIG. 1A, prior art full-rail differential logic circuit 100 included six transistors: PFET 105, PFET 107, PFET 109, PFET 115, PFET 117 and NFET 121. Prior art full-rail differential logic circuit 100 also included: OUT terminal 111 coupled to a terminal 178 of a base logic portion 123A of a logic block 123 and OUTBAR terminal 113 coupled to a terminal 179 of a complementary logic portion 123B of logic block 123. Prior art full-rail differential logic circuit 100 is activated from a clock signal CLKA. As shown in FIG. 1A, signal CLKA was supplied to: gate 116 of PFET 115; gate 118 of PFET 117; gate 129 of PFET 109; and gate 122 of NFET 121.
Prior art full-rail differential logic circuit 100 worked reasonably well, however, during the evaluation phase, prior art full-rail differential logic circuit 100 drew excess power unnecessarily as the relevant inputs, 151 or 153, to logic network 123 were transitioning low to shut off the path of one of the complementary output terminals, out terminal 111 or outBar terminal 113, to ground. The high output terminal, out terminal 111 or outBar terminal 113, therefore experienced a “dip” during the transition when the inputs 151 or 153 switched from high to low and a short circuit current, or crossbar current, path was established from Vdd 102 to ground. This “dip” was undesirable and resulted in significant power being wasted.
In addition, the structure of prior art full-rail differential logic circuit 100 was particularly susceptible to noise. This problem was extremely undesirable, and damaging, since, typically, multiple prior art full-rail differential logic circuits 100 were cascaded in long chains (not shown) of prior art full-rail differential logic circuits 100. In these chain configurations, the susceptibility of prior art full-rail differential logic circuit 100 to noise meant that each successive stage of the chain contributed additional noise and was even more adversely affected by the noise than the previous stage. Consequently, a few stages into a chain of prior art full-rail differential logic circuits 100, noise became the dominant factor in the chain.
In addition, as noted above, since prior art full-rail differential logic circuit 100 was a dual rail logic circuit, requiring an output OUT 111 and a complementary output OUTBAR 113, in the prior art, logic block 123 had to include both a base logic function, via base logic portion 123A of logic block 123, such as an AND gate, OR gate, XOR gate, etc. and the complementary logic function, via complementary logic portion 123B of logic block 123, such as a NAND gate, NOR gate, XNOR gate, etc.
FIG. 1B shows one particular embodiment of a prior art full-rail differential logic circuit 100A that includes a base logic portion 123A that is an AND gate and a complementary logic portion 123B that is a NAND gate. As shown in FIG. 1B, AND gate 123A includes NFET 161 and NFET 163 connected in series. Input 151 is coupled to the control electrode, or gate, of NFET 161 and input 153 is coupled to the control electrode or gate of NFET 163. As also shown in FIG. 1B, NAND gate 123A includes NFET 171 and NFET 173 connected in parallel. Input 151BAR is coupled to the control electrode, or gate, of NFET 171 and input 153BAR is coupled to the control electrode or gate of NFET 173. Consequently, in the prior art, four transistors were required to provide the output OUT 111 and its complementary output OUTBAR 113.
This need in the prior art to include both a base logic function and its complementary logic function resulted in an increase in power usage, an increase in space used, an increase in design complexity, and an increase in heat production.
What is needed is a method and apparatus for creating full-rail differential logic circuits that are more flexible, more space efficient and more reliable than prior art full-rail differential logic circuits, do not experience the large “dip” experienced by prior art full-rail differential logic circuit 100 and is therefore more power efficient. In addition, it is desirable to have a full-rail differential logic circuit that is more resistant to noise than prior art full-rail differential logic circuit 100.